1. Field of the Invention
The invention pertains to a flat panel display, and more particularly, to a driving circuit including a shift register and a flat panel display device using the same.
2. Description of the Related Art
A cathode ray tube (CRT) is used for a display device such as television and a monitor. However, the CRT has some drawbacks such as heavy weight, large volume and high driving voltage. Accordingly, flat panel display (FPD) devices having portability and low power consumption have been the subject of much recent research due to the coming of the information age. Among the various types of FPD devices, liquid crystal display (LCD) devices and electroluminescent display (ELD) devices are widely used as monitors for notebook computers and desktop computers because of their high resolution, ability to display colors and superiority in displaying moving images.
In general, an LCD device includes two substrates disposed such that respective electrodes of the two substrates face each other. A liquid crystal layer is interposed between the respective electrodes. When a voltage is applied between the two electrodes, an electric field is generated. The electric field modulates the light transmittance of the liquid crystal layer by reorienting the liquid crystal molecules, thereby displaying images in the LCD device. On the other hand, an ELD device uses an electroluminescence phenomenon such that a light is emitted when an electric field over a critical intensity is applied to a fluorescent material. The ELD device is classified into an inorganic type and an organic type according to source exciting carriers. An organic electroluminescent display (OELD) device is widely used because of its superiority in displaying a full color image and a moving image. In addition, the OELD device has no limit in a viewing angle and has a high brightness and a low driving voltage.
FPD devices such as LCD devices and OELD devices include a circuit unit converting RGB data and several control signals of an external driving system into proper electric signals, and a display panel displaying images using the electric signals. In general, the circuit unit is formed on a substrate different from the display panel and has a gate driver and a data driver.
Recently, an active matrix type display panel where a plurality of pixel regions are disposed in matrix and a switching element such as a thin film transistor (TFT) is formed in each pixel region is widely used. The TFT is fabricated through the repetition of photolithographic processes. While the TFT in the pixel region is fabricated, a part of a driving circuit may be formed at the periphery of the pixel region. Since the driving circuit is partially formed in the display panel without the increase of photolithographic processes, a fabrication cost is reduced. Specifically, a gate driver having a relatively low driving frequency may be formed in the display panel with a high reliability.
FIG. 1 is a schematic plan view showing an active matrix type flat panel display device having a gate driver according to the related art. In FIG. 1, an active matrix type display device 10 includes a display panel 20 and a circuit unit 30 driving the display panel 20. The display panel 20 have a pixel array 22 including gate lines (not shown), data lines crossing the gate lines (not shown) to define a plurality of pixel regions, and a pixel TFT (not shown) connected to the corresponding gate and data lines, and a gate driver 24 including a plurality of driving TFTs connected to the gate lines. Since the plurality of driving TFTs are simultaneously formed with the pixel TFTs, an additional photolithographic process is not required. The circuit unit 30 includes a source circuit 32 generating several driving signals and a data driver 34 connected to the source circuit 32. The data driver 34 may have a tape carriage package (TCP) type where a driver integrated circuit (IC) 34a is formed on a flexible printed circuit (FPC).
FIG. 2 is a schematic block diagram showing the gate driver 24 of FIG. 1 according to the related art. In FIG. 2, the gate driver 24 includes a plurality of related art shift register stages “SRS1R,” “SRS2R” and “SRS3R,” and a clock line 26 supplying a clock to the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R.” A plurality of gate lines “g1,” “g2” and “g3” of the pixel array 22 (of FIG. 1) are connected to output terminals of the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R,” respectively, and the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R” sequentially supply output signals to the plurality of gate lines “g1,” “g2” and “g3.” Since each output terminal of the shift register stage is connected to an input terminal of the next shift register stage, the gate signal of each shift register stage is used as a start signal of the next shift register stage.
FIG. 3 is a timing chart showing output signals of the gate driver 24 according to the related art. In FIG. 3, the plurality of related art shift register stages “SRS1R,” “SRS2R” and “SRS3R” (of FIG. 2) sequentially supply output signals “Vg1,” “Vg2,” and “Vg3” respectively to the plurality of gate lines “g1,” “g2” and “g3” (of FIG. 2). Accordingly, a plurality of pixel TFTs connected to the plurality of gate lines “g1,” “g2” and “g3,” respectively, are sequentially turned on. Since the gate driver 24 generates only a square wave, the output signals of the gate driver 24 have a simple shape and the shape of the output signals is not changed after the gate driver 24 is formed.
FIG. 4 is a schematic circuit diagram showing a gate driver using two-phase clocks in a display panel for a flat panel display device according to the related art and FIG. 5 is a schematic timing chart showing signals input to and output from the gate driver of FIG. 4.
In FIG. 4, the gate driver includes a plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R” using two-phase clocks CLK1 and CLK2. Each of the shift register stages “SRS1,” “SRS2” and “SRS3” includes a shift register unit “SRU1,” “SRU2” or “SRU3,” and first and second transistors “T1” and “T2” connected to each other in series and to the corresponding shift register unit. Output signals “Vg1,” “Vg2” and “Vg3” are output from connection portions between the first and second transistors “T1” and “T2” to a plurality of gate lines “g1,” “g2” and “g3” in a pixel array, respectively. In the first shift register stage “SRS1R,” the first transistor “T1” is connected to a first clock line 26a and the second transistor “T2” is grounded. In the second shift register stage “SRS2R,” the first transistor “T1” is connected to a second clock line 26b and the second transistor “T2” is grounded. Similarly, the first transistors “T1” of the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R” are alternately connected to the first and second clock lines 26a and 26b, and the second transistors “T2” of the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R” are grounded.
Gate electrodes of the first and second transistors “T1” and “T2” are connected to Q node and Qb node of the corresponding shift register unit “SRU1,” “SRU2” and “SRU3,” respectively. When the Q node has a high state and the Qb node has a low state, the first transistor “T1” is turned on and the second transistor “T2” is turned off. Accordingly, each of the shift register stages “SRS1R,” “SRS2R” and “SRS3R” outputs a corresponding clock signal of one of the first and second clock lines 26a and 26b connected to the first transistor “T1” toward the corresponding gate line “g1,” “g2” or “g3.”
As shown in FIG. 5, two-phase first and second clocks “CLK1” and “CLK2” of the first and second clock lines 26a and 26b alternate with each other. Since a Q1 node of the first shift register unit “SRU1” has a high state according to a start signal and the second clock “CLK2,” the first shift register stage “SRS1R” outputs the first clock “CLK1.” When the shift register unit uses two-phase first and second clocks “CLK1” and “CLK2,” a state of Q node may be changed from high to low by the clock corresponding to the next stage.
FIG. 6 is a schematic circuit diagram showing a gate driver using three-phase clocks in a display panel for a flat panel display device according to the related art and FIG. 7 is a schematic timing chart showing signals input to and output from the gate driver of FIG. 6.
In FIG. 6, the gate driver includes a plurality of related art shift register stages “SRS1R,” “SRS2R” and “SRS3R” using three-phase clocks CLK1˜CLK3. Each of the shift register stages “SRS1R,” “SRS2R” and “SRS3R” includes a shift register unit “SRU1,” “SRU2” or “SRU3,” and first and second transistors “T1” and “T2” connected to each other in series and to the corresponding shift register unit. Output signals “Vg1,” “Vg2” and “Vg3” are output from connection portions between the first and second transistors “T1” and “T2” to a plurality of gate lines “g1,” “g2” and “g3” in a pixel array, respectively. In the first shift register stage “SRS1R,” the first transistor “T1” is connected to a first clock line 26a (CLK1) and the second transistor “T2” is grounded. The first transistor “T1” is connected to a second clock line 26b (CLK2) and the second transistor “T2” is grounded in the second shift register stage “SRS2R”; and the first transistor “T1” is connected to a third clock line 26c (CLK3) and the second transistor “T2” is grounded in the third shift register stage “SRS3R.” In this manner, the first transistors “T1” of the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R” are alternately connected to the first, second and third clock lines 26a, 26b and 26c, and the second transistors “T2” of the plurality of shift register stages “SRS1R,” “SRS2R” and “SRS3R” are grounded.
Gate electrodes of the first and second transistors “T1” and “T2” are connected to Q node and Qb node of the corresponding shift register unit “SRU1,” “SRU2” or “SRU3,” respectively. When the Q node has a high state and the Qb node has a low state, the first transistor “T1” is turned on and the second transistor “T2” is turned off in the shift register stage. Accordingly, each of the shift register stages “SRS1R,” “SRS2R” and “SRS3R” outputs a corresponding clock signal of one of the first, second and third clock lines 26a, 26b and 26c connected to the first transistor “T1” toward the corresponding gate line “g1,” “g2” or “g3.”
As shown in FIG. 7, the three-phase first, second and third clocks “CLK1,” “CLK2” and “CLK3” of the first, second and third clock lines 26a, 26b and 26c alternately have a high state. Since a Q1 node of the first shift register unit “SRU1” has a high state according to a start signal and the third clock “CLK3,” the first shift register stage “SRS1R” outputs the first clock “CLK1.” When the first shift register unit uses three-phase first, second and third clocks “CLK1,” “CLK2” and “CLK3,” a state of Q1 node may be changed from high to low by the second clock “CLK2.” Accordingly, the second clock “CLK2” is used as a disable signal of the first shift register unit “SRU1.” When clocks having a phase over three are used, a state change time of Q node and Qb node is easily controlled.
As discussed above, the related art shift register uses one of two-phase, three-phase and four-phase clocks of a square wave shape. However, the output signals of the related art shift register have a simple shape and the shape of the output signals can not be changed once the related art shift register is formed. Accordingly, a gate driver including the related art shift register does not have various functions. In addition, since a plurality of transistors are required, a reliability of the gate driver is reduced.